1. Field of the Invention
The present invention relates to a power network simulation and analysis tool for testing the reliability of the physical designs of integrated circuit semiconductor chips.
2. Related Art
A highly specialized field, commonly referred to as "electronic design automation" (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Indeed, it has now come to the point where the design process has become so overwhelming that the next generation of integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
After the circuit for a new semiconductor chip has been designed and physically laid out, there still remains extensive testing which must be performed to verify that this new design and layout works properly. Different combinations of test vectors are applied as inputs to the design in order to check that the outputs are correct. In the past, many prior art simulation and verification software tools assumed constant power supply voltage sources. This approach was deficient because although the design might be functioning perfectly under the assumption of constant power supply sources, it might, nevertheless, still not meet specifications due to hidden voltage drop and electro-migration problems in interconnect wires. In real life, each of the transistors of a semiconductor circuit consumes a small amount of power (during the logic switching period). Individually, the voltage drop in the power network attributable to a single transistor is negligible. However, due to rapid advances in semiconductor technology, today's chips can contain upwards of ten million or more transistors. The cumulative effect of all these voltage drops may lead to serious performance degradation or even critical failures. For example, a transistor might be specified to be a logic "0" from 0.0 to 0.7 volts and to be a logic "1" from 3.3 to 2.1 volts. However, due to the voltage drops in the power network, a transistor output might not switch to those specified ranges and thus results in a logic error. And even if a voltage-tolerant CMOS process is used whereby the transistor has more noise margin, its switching speed is detrimentally impacted. Higher power supply voltages makes transistors switch faster, whereas lower voltages makes them switch more slowly. Consequently, if the voltage in a power network of a circuit drops below a critical level, the speed of that circuit might be reduced to an unacceptable rate.
Another problem which might arise relates to electro-migration. It has been established that high current density can cause the metal in the lines distributing the power through the semiconductor chip to migrate along the path of the current flow. Eventually, over a period of time (e.g., several years), this electro-migration can result in an open circuit so that power is cut off from parts of the IC, thereby causing the IC to fail. The electro-migration may even result in a short circuit which also causes the IC to fail.
Thus, it would be prudent to test for any potential power distribution problems as part of the overall simulation and verification process. However, testing a circuit with millions of transistors is an extremely complex and time-consuming process. It requires expert knowledge and highly skilled EDA specialists. Furthermore, it requires the dedication of a powerful and expensive computer with gigabytes of memory. Indeed, advances in semiconductor technology has led to sub-micron designs having even greater numbers of transistors being crammed into ever greater densities at higher levels of complexities which threaten the capability of today's most powerful computers to simulate.
Prior art reliability simulation tools are often based on dynamic transistor-level simulation. While these dynamic reliability simulation tools offer a high degree of accuracy in simulation results, the requirement of transistor-level simulation adversely impacts simulation speed and thus lowers the overall performance of the simulation tools. Consequently, these dynamic transistor-level reliability simulation tools have limited practical applications and are typically used only by chip designers who are willing and able to strive for high accuracy at the expense of extended design cycles. Moreover, the stringent details required in transistor-level simulation also impose capacity limitations on the circuit designs that can be simulated using dynamic simulation tools. As design complexities continue to increase, the suitability and applicability of these dynamic simulation tools will become even more severely limited.
Alternatively, prior art gate-level logic simulation tools are used by many designers to estimate the power consumption of their circuit designs. Gate-level logic simulation is typically based on the node activities that occur during a simulation run of the circuit, and gate-level simulation tools offer better performance, in terms of both simulation speed and capacity limitation, over transistor-level simulation tools. Nevertheless, gate-level simulation tools cannot serve as practical alternatives to transistor-level simulation tools for reliability analysis because gate-level simulation tools yield results that lack the level of accuracy and granularity essential to reliability analysis. Thus, use of prior art gate-level logic simulation tools is generally limited to power estimation and is typically inapplicable to reliability simulation.
Thus, there exists a need for a reliability analysis tool for simulating and verifying gigantic power network of multi-million transistor sub-micron IC designs which does not require prohibitive simulation time to generate results despite the high complexity of today's deep sub-micron IC designs and which does not deliver results of such low granularity that the results are unsuitable for reliability analysis.